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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11141-1E
MEMORY
Un-buffered
16 M x 72 BIT SYNCHRONOUS DYNAMIC RAM DIMM
MB8516S072CZ-102/-103/-102L/-103L
168-pin, 4 Clock, 2-bank, based on 8 M x 8 Bit SDRAMs with SPD s DESCRIPTION
The Fujitsu MB8516S072CZ is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of eighteen MB81F64842C devices which organized as four banks of 8 M x 8 bits and a 2Kbit serial EEPROM on a 168-pin glass-epoxy substrate. The MB8516S072CZ features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB8516S072CZ is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface is needed.
s PRODUCT LINE & FEATURES
Parameter CL-tRCD-tRP Clock Frequency Burst Mode Cycle Time Output Valid from Clock Two Banks Active Power Dissipation Self Refresh Mode MB8516S072CZ-102/-102L 2-2-2 clk min. 100 MHz max. 10 ns min. 6 ns max. (CL = 2) 6642 mW max. 64.8 mW max. (std. power) 32.4 mW max. (low power) * * * * * MB8516S072CZ-103/-103L 3-2-2 clk min. 100 MHz max. 10 ns min. 6 ns max. (CL = 3) 6642 mW max. 64.8 mW max. (std. power) 32.4 mW max. (low power)
* Un-buffered 168-pin DIMM Socket Type (Lead pitch: 1.27 mm) * Conformed to JEDEC Standard (4 CLK) * Organization: 16,777,216 words x 72 bits * Memory: MB81F64842C (8 M x 8, 4-bank) x 18 pcs * 3.3 V 0.3 V Supply Voltage * All input/output LVTTL compatible * Conformed to Intel PC/100 spec
4096 Refresh Cycle every 65.6 ms Auto and Self Refresh CKE Power Down Mode DQM Byte Masking (Read/Write) Serial Presence Detect (SPD) with Serial EEPROM: Intel SPD spec Rev 1.2A Format * Module size: 1.375" (height) x 5.25" (length) x 0.157" (thickness)
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MB8516S072CZ-102/-103/-102L/-103L
s PACKAGE
168-pin plastic DIMM (socket type)
(MDS PP ) (MDS-168P-P39)
Package and Ordering Information
- 168-pin DIMM, order as MB8516S072CZ-xxxDG (DG = std. power ver., Gold Pad) MB8516S072CZ-xxxLDG(LDG = low power ver., Gold Pad)
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MB8516S072CZ-102/-103/-102L/-103L
s PIN ASSIGNMENTS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Signal Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS N.C. N.C. VCC WE DQMB0 Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Signal Name DQMB1 CS0 N.C. VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 VSS N.C. CS2 DQMB2 DQMB3 N.C. VCC N.C. N.C. CB2 CB3 VSS DQ16 DQ17 Pin No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal Name DQ18 DQ19 VCC DQ20 N.C. N.C. CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 N.C. N.C. (WP) SDA SCL VCC Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal Name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 Pin No. Signal Name Pin No. Signal Name
113 DQMB5 114 CS1 115 RAS 116 VSS 117 A1 118 A3 119 A5 120 A7 121 A9 122 BA0 123 A11 124 VCC 125 CLK1 126 N.C. 127 VSS 128 CKE0 129 CS3 130 DQMB6 131 DQMB7 132 N.C. 133 VCC 134 N.C. 135 N.C. 136 CB6 137 CB7 138 VSS 139 DQ48 140 DQ49
141 DQ50 142 DQ51 143 VCC 144 DQ52 145 N.C. 146 N.C. 147 N.C. 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VCC 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 CLK3 164 N.C. 165 SA0 166 SA1 167 SA2 168 VCC
100 DQ44 101 DQ45 102 VCC 103 DQ46 104 DQ47 105 CB4 106 CB5 107 VSS 108 N.C. 109 N.C. 110 VCC 111 CAS 112 DQMB4
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MB8516S072CZ-102/-103/-102L/-103L
TOP VIEW
133.37 mm
D0 34.93 mm
D1
D2
D3
D4
D5
D6
D7
D8
PLANE 0 1 10 11 40 41 84
85
94
95
124 125 PLANE 1
168
D9
D 10
D 11
D 12
D 13
D 14
D 15
D 16
D 17
(MDS-168P-P39)
s PIN DESCRIPTIONS
Symbol A0 to A11 BA0, BA1 RAS CAS WE DQMB0 to DQMB7 CLK0 to CLK3 CKE0, CKE1 CS0 to CS3 I/O I I I I I I I I I Function Address Input Bank Select (Bank Address) Row Address Strobe Column Address Strobe Write Enable Data (DQ) Mask Clock Input Clock Enable Chip Select Symbol DQ0 to DQ63 CB0 to CB7 VCC VSS N.C. SA0 to SA2 SCL SDA WP I/O Function I/O Data Input/Data Output I/O Data I/O for ECC -- -- -- I I I/O -- Power Supply (+3.3 V) Ground (0 V) No Connection Serial PD Address Input Serial PD Clock Serial PD Address/Data Input/Output Serial PD Write Protect
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MB8516S072CZ-102/-103/-102L/-103L
s SERIAL-PD INFORMATION
Byte 0 Function Described Hex Value -102/ -103/ 102L 103L 80h 80h 08h 04h 0Ch 09h 02h 48h 00h 01h A0h 60h 02h 80h 08h 08h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 18h 00h 00h 00h 00h 00h 00h 00h 64h FFh -- 08h 04h 0Ch 09h 02h 48h 00h 01h A0h 60h 02h 80h 08h 08h 01h 8Fh 04h 06h 01h 01h 00h 0Eh F0h 80h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 88h 00h 00h 00h 00h 00h 00h 00h 64h FDh --
128 Byte Defines Number of Bytes Written into Serial Memory at Module Manufacture 1 256 Byte Total Number of Bytes of SPD Memory Device 2 SDRAM Fundamental Memory Type 3 12 Number of Row Addresses 4 9 Number of Column Addresses 5 2 bank Number of Module Banks 6 72 bit Data Width 7 +0 Data Width (Continuation) 8 LVTTL Interface Type 9 10/10 ns SDRAM Cycle Time (Highest CAS Latency) 10 6/6 ns SDRAM Access from Clock (Highest CAS Latency) 11 ECC DIMM Configuration Type 12 Self, Normal Refresh Rate/Type 13 x8 Primary SDRAM Width 14 x8 Error Checking SDRAM Width 15 1 Cycle Minimum Clock Delay for Back to Back Random Column Addresses 16 1, 2, 4, 8, Page Burst Lengths Supported 17 4 bank Number of Banks on Each SDRAM Device 18 2, 3 CAS Latency Supported 19 0 CS Latency 20 0 Write Latency 21 UN-buffer SDRAM Module Attributes 22 *1 SDRAM Device Attributes : General 23 10/15 ns SDRAM Cycle Time (2nd. Highest CAS Latency) 24 6/8 ns SDRAM Access from Clock (2nd. Highest CAS Latency) 25 No Support SDRAM Cycle Time (3rd. Highest CAS Latency) 26 No Support SDRAM Access from Clock (3rd. Highest CAS Latency) 27 20/20 ns Minimum Row Precharge Time (tRP) Row Activate to Row Activate Minimum (tRRD) 28 20/20 ns RAS to CAS Delay Min. (tRCD) 29 20/20 ns Minimum RAS Pulse Width 30 50/50 ns Module Bank Density 31 64 MByte Command and Address Signal Input Setup Time 32 2 ns Command and Address Signal Input Hold Time 33 1 ns Data Signal Input Setup Time 34 2 ns Data Signal Input Hold Time 35 1 ns 36 to 61 Unused Storage Locations -- SPD Data Revision Code 62 1.2 Checksum for Byte 0 to 62 63 *2 64 to 71 Manufacturer's JEDEC ID Code Per JEP-108E Optional Manufacturing Location 72 Optional 73 to 90 Manufacturer's Part Number Optional 91 to 92 Revision Code Optional 93 to 94 Manufacturing Data Optional 95 to 98 Assembly Serial Number Optional 99 to 125 Manufacturer Specific Data Optional Intel Specification Frequency 126 100 MHz Intel Specification Details for 100 MHz Support 127 CL = 2, 3 / 3 Unused Storage Locations 128+ -- Note: Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken. *1. Byte 22: SDRAM Device Attributes Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Supports Supports Supports Lower VCC Upper VCC Write 1 Precharge AutoTBD TBD tolerance tolerance /Read Burst All Precharge
0 0 0 0 1 1 1 *2. Byte 63: Checksum for Byte 0 to 62 This byte is the checksum for Byte 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of Byte 0 through 62. 5
Bit0 Supports Early RAS Precharge 0
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MB8516S072CZ-102/-103/-102L/-103L
BLOCK DIAGRAM
CS0 CS1 DQM0 DQ (7:0) 10 DQM1 DQ (15:8) 10 8M x 8 D4 10 CS2 CS3 DQM2 DQ (23:16) 10 DQM3 DQ (31:24) 10 VCC RAS 10 K CKE1 CKE0 CKE: SDRAM D9-17 CKE: SDRAM D0-8 SERIAL PD BA0 SCL SDA SA2 SA1 SA0 N.C. (WP) CLK1 47 K VSS VCC C VSS VSS: SDRAM CLK3 VCC: SDRAM CLK2 10 CLK: SDRAM D14,15 CLK: SDRAM D16, 17 +3.3 pF 10 CLK: SDRAM D5, 6 CLK: SDRAM D7, 8 +3.3 pF 10 CLK: SDRAM D9,10 CLK: SDRAM D11, 12, 13 CLK0 BA1 10 CLK: SDRAM D0,1 CLK: SDRAM D2, 3, 4 A13: SDRAM D0-17 A12: SDRAM D0-17 CAS WE A (11:0) CAS: SDRAM D0-17 WE: SDRAM D0-17 A (11:0): SDRAM D0-17 RAS: SDRAM D0-17 8M x 8 D8 8M x 8 D17 DQM7 DQ (63:56) 10 8M x 8 D6 8M x 8 D15 DQM6 DQ (55:48) 10 8M x 8 D7 8M x 8 D16 8M x 8 D5 8M x 8 D14 8M x 8 D13 8M x 8 D2 8M x 8 D11 DQM5 DQ (47:40) 10 8M x 8 D0 8M x 8 D9 DQM4 DQ (39:32) 10 8M x 8 D3 8M x 8 D12 8M x 8 D1 8M x 8 D10
CB (7:0)
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MB8516S072CZ-102/-103/-102L/-103L
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage* Input Voltage* Output Voltage* Storage Temperature Power Dissipation Output Current (D.C.) * : Voltages referenced to VSS (= 0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC VIN VOUT TSTG PD IOUT Value Min. -0.5 -0.5 -0.5 -55 -- -50 Max. +4.6 +4.6 +4.6 +125 18 +50 Unit V V V C W mA
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, All Inputs Input Low Voltage, All Inputs Ambient Temperature Notes *1 *1, 2 *1, 3 Symbol VCC VSS VIH VIL TA Value Min. 3.0 0 2.0 -0.5 0 Typ. 3.3 0 -- -- -- Max. 3.6 0 VCC +0.5 0.8 +70 Unit V V V V C
*1. Voltages referenced to VSS (=0V) *2. Overshoot limit: VIH (max.) = VCC +1.5 V with a pulse-width 5 ns. *3. Undershoot limit: VIL (min.) = -1.5 V with a pulse-width 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB8516S072CZ-102/-103/-102L/-103L
s CAPACITANCE
(VCC = +3.3 V, f = 1 MHz, TA = +25C) Parameter A0 to A11, BA0, BA1 RAS, CAS, WE CS0 to CS3 Input Capacitance CKE0, CKE1 CLK0 to CLK3 DQMB0 to DQMB7 SCL SA0, SA1, SA2 SDA Input/Output Capacitance DQ0 to DQ63 CB0 to CB7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CSCL CSA CSDA CDQ CCB Value Min. -- -- -- -- -- -- -- -- -- -- -- Max. 106 103 37 62 46 24 7 7 7 18 18 Unit pF pF pF pF pF pF pF pF pF pF pF
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MB8516S072CZ-102/-103/-102L/-103L
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3
Value Parameter
Notes Symbol
Condition
Max. Min. std. ver. low ver.
Unit
ICC1S
Operating Current (Average Power Supply Current)
*4
Burst Length = 4, tRC = min for BL = 4, tCK = min, One Bank Active, Outputs Open, Address changed up to 3 times during tRC(min.), 0 V VIN VCC Burst Length = 4 (each Bank), tRC = min for BL = 4 (each Bank), tCK = min, Two Banks Active, Outputs Open, Address changed up to 3 times during tRC(min.), 0 V VIN VCC CKE = VIL, tCK = min, All Banks Idle, Power Down Mode, 0 V VIN VCC CKE = VIL, CLK = VIH or VIL, All Banks Idle, Power Down Mode, 0 V VIN VCC CKE = VIH, tCK = min, All Banks Idle, NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles, 0 V VIN VCC CKE = VIH, CLK = VIH or VIL, All Banks Idle, Input Signals are Stable, 0 V VIN VCC
--
1080
mA
ICC1D
--
1845
mA
ICC2P
--
36
18
mA
ICC2PS
--
18
9
mA
Precharge Standby Current (Power Supply Current)
*4 ICC2N
--
270
mA
ICC2NS
--
36
mA
(Continued)
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MB8516S072CZ-102/-103/-102L/-103L
(Continued)
Value Parameter
Notes
Symbol
Condition
Max. Min. std. ver. 36 low ver. 18
Unit
ICC3P
CKE = VIL, tCK = min, Any Bank Active, 0 V VIN VCC CKE = VIL, CLK = VIH or VIL, Any Bank Active, 0 V VIN VCC CKE = VIH, tCK = min, Any Bank Active, NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles, 0 V VIN VCC CKE = VIH, CLK = VIH or VIL, Any Bank Active, 0 V VIN VCC tCK = min, Gapless data, Burst Length = 4, Outputs open, Multiple-banks Active, 0 V VIN VCC Auto Refresh, tCK = min, tRC = min, 0 V VIN VCC Self-refresh, tCK = min, CKE 0.2 V, 0 V VIN VCC 0 V VIN VCC All other pins not under test = 0 V Output is disabled (Hi-Z) 0 V VIN VCC IOH = -2.0 mA IOL = +2.0 mA
--
mA
ICC3PS
--
18
9
mA
Active Standby Current (Power Supply Current)
*4 ICC3N
--
450
mA
ICC3NS
--
36
mA
Burst Mode Current (Average Power Supply Current)
*4
ICC4
--
900
mA
Auto-refresh Current (Average Power Supply Current) Self-refresh Current (Average Power Supply Current) Input Leakage Current (All Inputs) Output Leakage Current LVTTL Output High Voltage LVTTL Output Low Voltage
*4
ICC5
--
4320
mA
*4
ICC6
--
18
9
mA
ILI ILO *5 *5 VOH VOL
-90 -20 2.4 --
90 20 -- 0.4
A A V V
Notes: *1. An initial pause (DESL on NOP) of 200 s is required after power-on followed by a minimum of eight Auto-refresh cycles. *2. Values of ICC1S, ICC1D and ICC4 are for when one side of the double-sided module is in standby mode (ICC2N)and the other side is in active. *3. DC characteristics is the Serial PD standby state (VIN = GND or VCC). *4. ICC depends on the output termination, load conditions, clock cycle rate and signal clock rate. The specified values are obtained with the output open and no termination resistors. *5. Voltages referenced to VSS (= 0 V) 10
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MB8516S072CZ-102/-103/-102L/-103L
s AC CHARACTERISTICS
(SDRAM Component Specifications) Notes 1, 2, 3 (1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.)
No. Parameter Notes CL = 2 CL = 3 Symbol tCK2 tCK3 tCH tCL tSI tHI CL = 2 *4, *5 CL = 3 tAC3 tLZ *6 CL = 2 CL = 3 tHZ2 tHZ3 tOH tREF tT tCKSP -- 0 3 3 3 -- 0.5 3 6 -- 6 6 -- 65.6 2 -- -- 0 3 3 3 -- 0.5 3 6 -- 8 6 -- 65.6 2 -- ns ns ns ms ns ns tAC2 MB8516S072CZ -102/-102L Min. 1 2 3 4 5 6 7 8 9 10 11 12 Clock Period Clock High Time Clock Low Time Input Setup Time Input Hold Time Output Valid from Clock (tCLK = min) Output in Low-Z Output in High-Z Output Hold Time Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time 10 10 3 3 2 1 -- Max. -- -- -- -- -- -- 6 MB8516S072CZ -103/-103L Min. 15 10 3 3 2 1 -- Max. -- -- -- -- -- -- 8 ns ns ns ns ns ns Unit
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MB8516S072CZ-102/-103/-102L/-103L
(2) BASE VALUES FOR CLOCK COUNT/LATENCY
No. 1 2 3 4 5 6 Parameter RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time Data-in to Precharge Lead Time CL = 2 7 Data-in to Active/Refresh Command Period CL = 3 8 9 Mode Register Set Cycle Time RAS to RAS Bank Active Delay Time tDAL3 tRSC tRRD *8 Notes Symbol *7 tRC tRP tRAS tRCD tWR tDPL tDAL2 MB8516S072CZ -102/-102L Min. 70 20 50 20 10 10 1 cyc + tRP 2 cyc + tRP 20 20 Max. -- -- 110000 -- -- -- -- -- -- -- MB8516S072CZ -103/-103L Unit Min. Max. 70 20 50 20 10 10 1 cyc + tRP 2 cyc + tRP 20 20 -- -- 110000 -- -- -- -- ns -- -- -- ns ns ns ns ns ns ns ns
(3) CLOCK COUNT FORMULA (*9)
Clock Base Value Clock Period (Round off a whole number)
(4) LATENCY (The latency values on these parameters are fixed regardless of clock period.)
No. 1 2 3 4 5 6 7 8 9 CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (min) CAS Bank Delay (min) CL = 2 CL = 3 CL = 2 CL = 3 Parameter Symbol MB8516S072CZ MB8516S072CZ -102/-102L -103/-103L ICKE IDQZ IDQD IOWD IDWD IROH2 IROH3 IBSH2 IBSH3 ICCD ICBD 1 2 0 2 0 2 3 2 3 1 1 1 2 0 2 0 2 3 2 3 1 1 Unit Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
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MB8516S072CZ-102/-103/-102L/-103L
Notes: *1. An initial pause (DESL on NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles. *2. 1.4 V or VREF is the reference level for measuring timing of signals. Transition times are measured between VIH (min) and VIL (max). *3. AC characteristics assume tT = 1 ns and 50 pF of capacitance load. *4. Assumes tRCD is satisfied. *5. tAC also specifies the access time at burst mode except for first access. *6. Specified where output buffer is no longer driven. *7. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP). *8. Operation within the tRCD (min) ensures that access time is determined by tRCD (min) +tAC (max) ; if tRCD is greater than the specified tRCD (min), access time is determined by tAC. *9. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *Source: See MB81F64842C Data Sheet for details on the electrical.
s AC OPERATING TEST CONDITION (Example of AC Test Load Circuit)
1.4 V
50
Z = 50 I/O
50 pF
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MB8516S072CZ-102/-103/-102L/-103L
s SERIAL PRESENCE DETECT(SPD) FUNCTION
1. PIN DESCRIPTIONS
SCL (Serial Clock) SCL input is used to clock all data input/output of SPD. SDA (Serial Data) SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output. SA0, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other.
2. SPD OPERATIONS
CLOCK and DATA CONVENTION Data states on the SDA can change only during SC L= Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig. 1 below. START CONDITION All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met. STOP CONDITION All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence.
Fig. 1 - START AND STOP CONDITIONS
SCL
SDA
START START = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High
STOP
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MB8516S072CZ-102/-103/-102L/-103L
ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices --namely up to eight modules-- on the bus. The eight addresses for eight SPD devices are defined by the state of the SA0, SA1 and SA2 inputs. The last bit of the slave address defines the operation to be performed. When R/W bit is "1", a read operation is selected, when R/W bit is "0", a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA0, SA1, and SA2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation. Fig. 2 - SLAVE ADDRESS
DEVICE TYPE IDENTIFIER DEVICE ADDRESS
1
0
1
0
SA2
SA1
SA0
R/W
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MB8516S072CZ-102/-103/-102L/-103L
3. READ OPERATIONS
CURRENT ADDRESS READ Internally the SPD contains an address counter that maintains the address of the last data accessed, incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = "1", the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 3 for the sequence of address, acknowledge and data transfer.
Fig. 3 - CURRENT ADDRESS READ
S T A R T SLAVE ADDRESS S T O P
BUS ACTIVITY : MASTER SDA LINE
BUS ACTIVITY : SPD
A C K
DATA
RANDOM READ Random Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = "1", the master must first perform a "dummy" write operation on the SPD. The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/ W bit = "1". This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 4 for the sequence of address, acknowledge and data transfer.
Fig. 4 - RANDOM READ
S T BUS ACTIVITY : A R MASTER T SDA LINE BUS ACTIVITY : SPD A C K A C K A C K S T A R T
SLAVE ADDRESS
WORD ADDRESS
SLAVE ADDRESS
S T O P
DATA
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MB8516S072CZ-102/-103/-102L/-103L
SEQUENTIAL READ Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" to address 0 and the SPD continues to output data for each acknowledge received.
Fig. 5 - SEQUENTIAL READ
SLAVE ADDRESS BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD A C K A C K A C K A C K S T O P
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+x)
4. DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Output Low Voltage Note: *1. Referenced to VSS. *1 Note Symbol SILI SILO SVOL Condition 0 V VIN VCC 0 V VOUT VCC IOL = 3.0 mA Value Min. -10 -10 -- Max. 10 10 0.4 Unit A A V
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MB8516S072CZ-102/-103/-102L/-103L
5. AC CHARACTERISTICS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR Value Min. -- -- -- 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 100 -- Max. 100 100 3.5 -- -- -- -- -- -- -- 1 300 -- -- 15 Unit
KHz
ns s s s s s s s ns s ns s ns ms
Fig. 6 - TIMING WAVEFORM
tF tR tLOW SCL tSU : STA tHD : DAT tHD : STA SDA (input) tAA SDA (output) tDH tSU : DAT tSU : STO
tHIGH
tBUF
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MB8516S072CZ-102/-103/-102L/-103L
s PACKAGE DIMENSION
168-pin plastic DIMM (socket type) (MDS-168P-P39)
133.350.13(5.250.005) 131.350.13(5.171.005) 128.930.13(5.076.005) C L 66.680.13(2.625.005) 65.680.13(2.586.005)
4-R1.270.10 (4-R.05.004)
3.00(.118)MIN.
4.00(.157)MAX.
4.000.10 (.157.004) 34.930.13 (1.375.005) 2-O3.000.05 (2-O.118.002) 4.00(.157)MIN.
1
84
"A" 3.000.13 (.118.005) Pin No.1 INDEX. 11.430.05 (.450.002) 1.27 -0.08 .050 -.003
+0.10 +.004
"B" 36.830.05 (1.450.002) 42.180.13 (1.661.005)
"C" 3.170.13 1.270.03 (.125.005) (.050.001) 54.610.05(2.150.002)
Details of "A" part
6.350.13 (.250.005) 2.000.10(.079.004) 1.000.05(.039.002)
C L 115.570.13(4.550.005) 127.350.13(5.014.005)
3.25(.128) 3.00(.118) Details of "B" part C L
168
6.350.13 (.250.005) 2.000.10(.079.004) 1.000.05(.039.002) 1.000.05 (.039.002) 0.25(.010)MAX.
17.780.13 22.250.13 (.700.005) (.876.005)
9.530.10 (.375.004)
C
1998 FUJITSU LIMITED M168039SC-1-1
85
3.25(.128) 3.00(.118) Details of "C" part 2.54(.100)TYP. NOTCHES FULL R
Dimension in mm (inches)
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MB8516S072CZ-102/-103/-102L/-103L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9812 (c) FUJITSU LIMITED Printed in Japan
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